(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to protect a dielectric layer, used for a non-volatile memory, (particularly in EEPROM) application, during fabrication of peripheral embedded memory devices.
(2) Description of Prior Art
Non-volatile memory applications are being fabricated featuring an oxidized nitride on silicon oxide (ONO), dielectric layer formed on an underlying floating gate structure. The data retention characteristics of the non-volatile memory device is partially influenced by integrity of top portion of the ONO dielectric layer, the thin top oxide component obtained via the oxidation of a top portion of a silicon nitride layer. The thin oxide component controls the barrier height between the nitride component of the ONO dielectric and an overlying control gate structure, minimizing the charge loss from the underlying floating gate. However when peripheral high and low voltage devices are integrated with the non-volatile memory device, the critical top oxide component of the ONO dielectric layer can be exposed to processing sequences which can result in unwanted removal of portions of the top oxide layer, resulting in data retention degradation.
This invention will describe process sequences featuring materials which allow capping and protection of the top oxide component of the ONO dielectric layer to be achieved, therefore avoiding oxide loss during specific processes used in the integration of peripheral memory devices with the non-volatile memory device. In addition the thickness of the top oxide can be increased, as depicted in a second iteration of this invention. Prior art such as Lai et al in U.S. Pat. No. 6,448,126, as well as Camerlenghi in U.S. Pat. No. 6,420,223, describe methods of protecting ONO layers during some subsequent processing sequences. However these prior art do not describe the novel process sequence offered in the present invention wherein disposable capping materials are employed to protect the thin top oxide component of an ONO dielectric layer present on the non-volatile device, during specific fabrication sequences used for embedded peripheral memory devices.
It is an object of this invention to integrate the fabrication of a non-volatile memory device with the fabrication of low voltage and high voltage complimentary metal oxide semiconductor (CMOS), devices.
It is another object of this invention to protect the dielectric layer located on the floating gate structure of the non-volatile memory device during hydrofluoric acid type procedures used with the fabrication sequence for the low and high voltage CMOS devices.
It is still another object of this invention to employ a disposable silicon nitride layer, or a disposable polysilicon layer, on the floating gate structure to protect the dielectric layer on the floating gate structure so that hydrofluoric acid type cleaning procedures can be used with the fabrication of the low and high CMOS devices, resulting in better gate oxide integrity (GOI).
In accordance with the present invention a method of integrating the fabrication of a non-volatile memory device with the fabrication of low voltage and high voltage complimentary metal oxide semiconductor (CMOS), devices, featuring the use of a capping layer used to protect the dielectric layer located on the floating gate structure of the non-volatile memory device, during hydrofluoric acid type procedures, either dilute hydrofluoric (DHF), or buffered hydrofluoric (BHF), performed during the fabrication sequence of the low and high voltage CMOS devices, is described. A first iteration of this invention entails the formation of the floating gate structure of the non-volatile device in a first region of a semiconductor substrate, followed by formation of an overlying oxidized silicon nitride on silicon oxide (ONO), dielectric layer. After deposition of a silicon nitride capping layer definition of the silicon nitride layer and of the ONO dielectric layer is only on the floating gate structure in the first region of the semiconductor substrate. After a hydrofluoric acid type pre-clean procedure a first gate insulator layer is thermally grown on exposed semiconductor portions in second and third regions, followed by removal of the first gate insulator layer from the second region of semiconductor substrate. The silicon nitride cap layer is then disposed, removed by dipping into phosphoric acid (H3PO4). After removal of the capping silicon nitride layer, located overlying the ONO dielectric layer located on the floating gate structure, another clean procedure, without hydrofluoric acid, is performed followed by the growth of a second gate insulator layer on the exposed portions of the second region of semiconductor substrate, with the second gate insulator layer thinner than the first gate insulator layer. Completion of integrated fabrication procedure is accomplished via simultaneous formation of a polysilicon control gate structure on the ONO dielectric layer of the non-volatile memory device located in the first region of the semiconductor substrate, and of polysilicon gate structures in the second and third regions of the low and high voltage CMOS devices respectfully.
A second iteration of this invention features definition of a polysilicon capping layer on an underlying ONO dielectric layer, located on a floating gate structure of a non-volatile memory device in a first region of a semiconductor substrate. After a hydrofluoric acid type pre-clean procedure a first oxidation procedure is performed resulting in the formation of a first gate insulator layer on second and third regions of the semiconductor substrate, while partial oxidation of a top portion of the polysilicon capping layer occurs. After removal of the first gate insulator layer from the second region of the semiconductor substrate via a buffered hydrofluoric (BHF) acid type procedure, a second oxidation procedure is performed resulting in the formation of a second gate insulator layer in the second region of the semiconductor substrate, with the second gate insulator layer thinner than the first gate insulator layer, and with the second oxidation procedure resulting in total oxidation of the polysilicon capping layer located on the ONO dielectric layer. This results in self removal of the disposable polysilicon cap layer. Again completion of the integrated fabrication procedure is accomplished via simultaneous formation of a polysilicon control gate structure on the oxidized polysilicon capping layer, located overlying the ONO dielectric layer of the non-volatile memory device, and of polysilicon gate structures on the second and third regions of the low and high voltage CMOS devices respectfully.